View 8180D18_816943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GS8180D18D-250/200/167/133/100
165-Bump BGA Commercial Temp Industrial Temp Features
* Simultaneous Read and Write SigmaQuadTM Interface * JEDEC-standard pinout and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * Burst of 4 Read and Write * 1.8 V +150/-100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ mode pin for programmable output drive strength * IEEE 1149.1 JTAG-compliant Boundary Scan * 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package * Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb Burst of 4 SigmaQuad SRAM
250 MHz-100 MHz 1.8 V VDD 1.8 V or 1.5 V I/O
of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
Clocking and Addressing Schemes
A Burst of 4 SigmaQuad SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O Burst of 4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a Burst of 4 RAM is always two address pins less than the advertised index depth (e.g., the 1M x 18 has a 256K addressable index).
SigmaRAMTM Family Overview
GS8180D18 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst
Parameter Synopsis
-250 tKHKH tKHQV 4.0 ns 2.1 ns -200 5.0 ns 2.3 ns -167 6.0 ns 2.5 ns -133 7.5 ns 3.0 ns -100 10 ns 3.0 ns
Rev: 2.03 10/2004
1/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
1M x 18 SigmaQuad SRAM--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 MCL/SA (72Mb) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--13 x 15 mm2 Body--1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. MCL = Must Connect Low 4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.03 10/2004
2/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Pin Description Table Symbol
SA NC R W BW0-BW1 K K C C TMS TDI TCK TDO VREF ZQ MCL D0-D17 Q0-Q17 VDD VDDQ VSS Note: NC = Not Connected to die or any other pin
Description
Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Must Connect Low Synchronous Data Inputs Synchronous Data Outputs Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input -- Input Input Input Input Input Input Input Input Input Input Output Input Input -- Input Output Supply Supply Supply
Comments
-- -- Active Low Active Low Active Low Active High Active Low Active High Active Low -- -- -- -- -- -- -- -- -- 1.8 V Nominal 1.8 or 1.5 V Nominal --
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM's bandwidth in half. A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM's
Rev: 2.03 10/2004
3/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation. - Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port. - Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM. - All address, data, and control inputs are sampled on clock edges. In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details. Burst of 4 SigmaQuad SRAM DDR Read The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. The four resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C, the rising edge of C after that, the next rising edge of C, and finally by the next rising edge of C.
Burst of 4 Double Data Rate SigmaQuad SRAM Read First
Read A
K K Address R W BWx D C C Q A A+1 A+2 A+3 B B+1 B+2 B+3 D D+1 D+2 C C+1 C+2 C+3 E E+1 A B C D E
NOP
Read B
Write C
Read D
Write E
NOP
Rev: 2.03 10/2004
4/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Burst of 4 SigmaQuad SRAM DDR Write The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K.
Burst of 4 Double Data Rate SigmaQuad SRAM Write First
Write A
K Kbar Address Rbar Wbar BWx bar D C Cbar Q C C+1 C+2 C+3 D A A+1 A+2 A+3 B B+1 B+2 B+3 B+3 A B C D
NOP
Write B
Read C
NOP
Read D
NOP
Special Functions
Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0-D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.
Rev: 2.03 10/2004
5/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2 Beat 3 Beat 4
BW0
0 1 0 1
BW1
1 0 0 0
D0-D8
Data In Don't Care Data In Don't Care
D9-D17
Don't Care Data In Data In Data In
Resulting Write Operation Beat 1 D0-D8
Written
Beat 1 D9-D17
Unchanged
Beat 2 D0-D8
Unchanged
Beat 2 D9-D17
Written
Beat 3 D0-D8
Written
Beat 3 D9-D17
Written
Beat 4 D0-D8
Unchanged
Beat 4 D9-D17
Written
Output Register Control SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.
Rev: 2.03 10/2004
6/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Example Four Bank Depth Expansion Schematic
R3 W3 R2 W2 R1 W1 R0 W0 A0-An K D1-Dn Bank 0 A W R K D C Q Bank 1 A W R K D C Q Bank 2 A W R K D C Q Bank 3 A W R K D C Q
C Q1-Qn Note: For simplicity BWn, K, and C are not shown.
Rev: 2.03 10/2004
7/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Burst of 4 SigmaQuad SRAM Depth Expansion
Read A Write B Read C Write D Read E Write F NOP
Rev: 2.03 10/2004
A B C D E F D D+1 D+2 D+3 B B+1 B+2 B+3 F F+1 F+2 A A+1 A+2 A+3 E E+1 E+2 C C+1 C+2 C+3
K
Kbar
Address
R1bar
R2bar
W1bar
W2bar
BWx bar Bank1
D Bank1
BWx bar Bank2
8/27
D Bank2
C Bank1
Cbar Bank1
Q Bank1
C Bank2
Cbar Bank2
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q Bank2
GS8180D18D-250/200/167/133/100
(c) 2002, GSI Technology
GS8180D18D-250/200/167/133/100
FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance.
Separate I/O Burst of 4 SigmaQuad SRAM Truth Table A
K (tn)
R
K (tn)
W
K (tn)
Previous Operation
K (tn-1)
Current Operation
K (tn)
D
K (tn+1)
D
K (tn+11/2)
D
K (tn+2)
D
K (tn+21/2)
Q
K (tn+1)
Q
K (tn+11/2)
Q
K (tn+2)
Q
K (tn+21/2)
X X X V V V V
1 1 X 1 0 X 0
1 X 1 0 X 0 X
Deselect Write Read Deselect Deselect Read Write
Deselect Deselect Deselect Write Read Write Read
X D2 X D0 X D0 D2
X D3 X D1 X D1 D3
-- -- -- D2 -- D2 --
-- -- -- D3 -- D3 --
Hi-Z Hi-Z Q2 Hi-Z Q0 Q2 Q0
Hi-Z Hi-Z Q3 Hi-Z Q1 Q3 Q1
-- -- -- -- Q2 -- Q2
-- -- -- -- Q3 -- Q3
Notes: 1. "1" = input "high"; "0" = input "low"; "V" = input "valid"; "X" = input "don't care" 2. "--" indicates that the input requirement or output state is determined by the next operation. 3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations. 4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. Users should not clock in metastable addresses.
Rev: 2.03 10/2004
9/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Byte Write Clock Truth Table BW
K (tn+1) T T F F F F
BW
K (tn+11/2) T F T F F F
BW
K (tn+2) T F F T F F
BW
K (tn+21/2) T F F F T F
Current Operation
K (tn) Write Dx stored if BWn = 0 in all four data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Dx stored if BWn = 0 in 3rd data transfer only Write Dx stored if BWn = 0 in 4th data transfer only Write Abort No Dx stored in any of the four data transfers
D
K (tn+1) D0 D0 X X X X
D
K (tn+11/2) D2 X D1 X X X
D
K (tn+2) D3 X X D2 X X
D
K (tn+21/2) D4 X X X D3 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more BWn = 0, then BW = "T", else BW = "F".
x18 Byte Write Enable (BWn) Truth Table BW0 BW1
1 0 1 0 1 1 0 0
D0-D8
Don't Care Data In Don't Care Data In
D9-D17
Don't Care Don't Care Data In Data In
Rev: 2.03 10/2004
10/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
State Diagram
Power-
Read NOP
READ
WRITE
Write NOP
READ Load New Read Address R Count = 0 Always READ R Count = 2
WRITE Load New Write Address W Count = 0 Always WRITE W Count = 2
READ R Count = 2
WRITE W Count = 2
DDR Read R Count = R Count + 1 READ R Count = 1 Always
DDR Write W Count = W Count + 1 WRITE W Count = 1
Always
Increment Read Address
Increment Write Address
Notes: 1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1. 2. "READ" refers to read active status with R = Low, "READ" refers to read inactive status with R = High. The same is true for "WRITE" and "WRITE". 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. 5. R Count is the read counter; Burst of 4 must complete 2 DDR reads. 6. W Count is the write counter; Burst of 4 must complete 2 DDR writes.
Rev: 2.03 10/2004
11/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature
Value
-0.5 to 2.9 -0.5 to VDD -0.5 to VDDQ -0.5 to VDDQ +0.5 ( 2.9 V max.) -0.5 to VDDQ +0.5 ( 2.9 V max.) +/-100 +/-100 125 -55 to 125
Unit
V V V V V mA dc mA dc
oC o
C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage 1.8 V I/O Supply Voltage 1.5 V I/O Supply Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
VDD VDDQ VDDQ TA TA
Min.
1.7 1.7 1.4 0 -40
Typ.
1.8 1.8 1.5 25 25
Max.
1.95 1.95 1.6 70 85
Unit
V V V C C
Notes
1 1 2 2
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V VDDQ 1.6 V (i.e., 1.5 V I/O) and 1.7 V VDDQ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 2.03 10/2004
12/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low VREF DC Voltage Note: Compatible with both 1.8 V and 1.5 V I/O drivers
Symbol
VIH (dc) VIL (dc) VREF (dc)
Min
VREF + 200
Max
VREF - 200
Units
mV mV V
Notes
1 1 1
VDDQ (min)/2
VDDQ (max)/2
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 400
Max
VREF - 400 5% VREF (DC)
Units
mV mV mV
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac) VREF VIL (ac)
Rev: 2.03 10/2004
13/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Undershoot Measurement and Timing
VIH VDD + 1.0 V VSS 50% VSS - 1.0 V 20% tKHKH VIL 50% VDD
Overshoot Measurement and Timing
20% tKHKH
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Output Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Notes: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2
AC Test Load Diagram
DQ 50 VT = VDDQ/2 RQ = 250 (HSTL I/O) VREF = 0.75 V
Rev: 2.03 10/2004
14/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Output Leakage Current
Symbol
IIL IOL
Test Conditions
VIN = 0 to VDD Output Disable, VOUT = 0 to VDDQ
Min.
-2 uA -2 uA
Max
2 uA 2 uA
Notes
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 Vss VDDQ - 0.2 Vss
Max.
VDDQ VDDQ/2 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/- 15% @ VOH = VDDQ/2 (for: 175 RQ 350). 2. IOL = (VDDQ/2) / (RQ/5) +/- 15% @ VOL = VDDQ/2 (for: 175 RQ 350). 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = -1.0 mA 6. IOL = 1.0 mA
Operating Currents
-250 Parameter Org Symbol 0C to 70C TBD TBD TBD TBD -40C to +85C TBD TBD TBD TBD 0C to 70C 460 mA 95 mA 130 mA 5 mA -200 -40C to +85C TBD TBD TBD TBD 0C to 70C 400 mA 85 mA 120 mA 5 mA -167 -40C to +85C TBD TBD TBD TBD 0C to 70C 340 mA 70 mA 115 mA 5 mA -133 -40C to +85C TBD TBD TBD TBD 0C to 70C 280 mA 65 mA 110 mA 5 mA -100 -40C to +85C TBD TBD TBD TBD Test Conditions
IDD Operating Current x18 IDDQ ISB1 x18 ISBQ1
R and W VIL Max. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min. R and W VIH Min. tKHKH tKHKH Min. All other inputs VIN VIL Max. or VIN VIH Min.
Chip Disable Current
Note: Power measured with output pins floating. Rev: 2.03 10/2004 15/27 (c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
AC Electrical Characteristics
Parameter K, K Clock Cycle Time C, C Clock Cycle Time K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse Width K Clock High to K Clock High C Clock High to C Clock High K Clock High to K Clock High C Clock High to C Clock High K, K Clock High to C, C Clock High Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data and Byte Write Input Setup Time Data and Byte Write Input Hold Time K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z K Clock High to Data Output High-Z C Clock High to Data Output High-Z Symbol tKHKH tCHCH tKHKL tCHCL tKLKH tCLCH tKHKH tCHCH tKHKH tCHCH tKHCH tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX tKHQV tCHQV tKHQX tCHQX tKHQX1 tCHQX1 tKHQZ tCHQZ -250
Min Max
-200
Min Max
-167
Min Max
-133
Min Max
-100
Min Max
Units ns ns ns ns ns
Notes
4.0 1.5 1.5 1.8 1.8 0 0.5 0.5 0.5 0.5 0.5 0.5 -- 0.5 0.5 0.5
-- -- --
5.0 1.9 1.9 2.2 2.2
-- -- --
6.0 2.4 2.4 2.7 2.7
-- -- -- -- -- 2.0 -- -- -- -- -- -- 2.5 -- -- 2.5
7.5 3.0 3.0 3.4 3.4 0 0.8 0.8 0.8 0.8 0.8 0.8 -- 1.2 1.2 --
-- -- -- -- -- 2.5 -- -- -- -- -- -- 3.0 -- -- 3.0
10 3.0 3.0 4.6 4.6 0 1.0 1.0 1.0 1.0 1.0 1.0 -- 1.2 1.2 --
-- -- --
4
1.8 -- -- -- -- -- -- 2.1 -- -- 2.1
0 0.6 0.6 0.6 0.6 0.6 0.6 -- 1.0 1.0 --
2.3 -- -- -- -- -- -- 2.2 -- -- 2.2
0 0.7 0.7 0.7 0.7 0.7 0.7 -- 1.2 1.2 --
3.0 -- -- -- -- -- -- 3.0 -- -- 3.0
ns ns ns ns ns ns ns ns ns ns ns 2 2,3 2,3 1 1
Notes: 1. These parameters apply to control inputs R and W. 2. These parameters are guaranteed by design and characterization. Not 100% tested. 3. These parameters are measured at 50mV from steady state voltage. 4. tKHKH Max is specified by tKHKH Min. tCHCH Max is specified by tCHCH Min.
Rev: 2.03 10/2004
16/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
K and K Controlled Read-Write-Read Timing Diagram
Read A KHKH
K
Write B KHKL KLKH
NOP
Write C
Read D
Write E
NOP
KHKHbar
Kbar
AVKH KHAX
Address A B C D E
BVKH KHBX
Rbar
BVKH KHBX
Wbar
KHBX BVKH
BWx bar
KHDX DVKH
D B B+1 B+2 B+3 C C+1 C+2 C+3 E E+1
KHQV KHQX1
Q A A+1 A+2
KHQZ KHQX
A+3 D D+1 D+2 D+3
Rev: 2.03 10/2004
17/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
C and C Controlled Read-Write-Read Timing Diagram
Read A KHKH K KHKHbar Kbar AVKH KHAX Address A BVKH KHBX Rbar BVKH KHBX Wbar KHBX BVKH BWx bar DVKH D C KLKH KHKH Cbar CHQX1 Q A CHQV A+1 A+2 A+3 CHQX B B+1 B+2 CHQZ B+3 KHKL KHKHbar C C+1 KHDX C+2 C+3 D D+1 B C D NOP KHKL KLKH Read B Write C NOP Write D NOP
Rev: 2.03 10/2004
18/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 2.03 10/2004
19/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
* * *
108
*
*
*
*
*
*
* *
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
*
* **
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 2.03 10/2004
20/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Tap Controller Instruction Set ID Register Contents
Die Revision Code Bit # x18 GSI Technology JEDEC Vendor ID Code Presence Register 0 1
Not Used
I/O Configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 011011001
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
Rev: 2.03 10/2004
21/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is Rev: 2.03 10/2004 22/27 (c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU BYPASS
Code
000 001 010 011 100 101 110 111
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 2.03 10/2004
23/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
0.6 * VDD -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV --
Max.
VDD +0.3 0.3 * VDD 1 100 1 -- 0.4 -- 100 mV
Unit Notes
V V uA uA uA V V V V 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be -1 V > Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
JTAG Port AC Test Load
50 VDDQ/2
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted.
Rev: 2.03 10/2004
24/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns
Rev: 2.03 10/2004
25/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Package Dimensions--165-Bump FPBGA (Package D; Variation 3)
A1 CORNER TOP VIEW BOTTOM VIEW O0.10 M C O0.25 M C A B O0.44~0.64 (165x) A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 1.0
150.05
14.0
A
0.53 REF 0.35 C
1.0
1.0
0.20 C
B 0.20(4x)
130.05
Rev: 2.03 10/2004
0.36~0.46 1.40 MAX.
0.36 REF
C
SEATING PLANE
26/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8180D18D-250/200/167/133/100
Ordering Information--GSI SigmaQuad SRAM Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18
Part Number1
GS8180D18D-250 GS8180D18D-200 GS8180D18D-167 GS8180D18D-133 GS8180D18D-100 GS8180D18D-250I GS8180D18D-200I GS8180D18D-167I GS8180D18D-133I GS8180D18D-100I
Type
SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM SigmaQuad SRAM
Package
1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3)
Speed (MHz)
250 200 167 133 100 250 200 167 133 100
TA3
C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS818x18D-200T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 2.03 10/2004
27/27
(c) 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

▲Up To Search▲

Price & Availability of 8180D18

	To Download 8180D18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .